Integration of electronic and optical components on a common substrate has long been the motivation of growing GaAs and Ge layers on silicon wafers. However, a lattice mismatch of ~4% creates dislocations that propagate through the epitaxial layers and ultimately degrade optical performance. Researchers at the University of New Mexico have investigated 3-D stress relief mechanisms unique to nanoscale islands and found a method of reducing strain energy in lattice-mismatched systems, called nanoheteroepitaxy (NHE). They began with a bigger challenge than GaAs, GaN on silicon where the lattice mismatch is typically 20%, and the results have been encouraging.

Figure 1 . Schematic cross-sectional view of NHE structure shows silicon islands, 10 to 300 nm in diameter and 360 or 900 nm in pitch. (Source: University of New Mexico)

While GaN is commonly grown directly on silicon, silicon on insulator (SOI) layers and sapphire, NHE introduces an array of nanoscale pillars sandwiched between the substrate and epitaxial layer to absorb strain energy. Though the concept of pillars is not new, sub-micron sizes are. In this case, the upper silicon layer of a <111> SOI wafer is patterned into an array of islands, 10 to 300 nm in diameter and 360 or 900 nm in pitch, using interferometric lithography (Fig 1). GaN is first grown selectively onto the silicon islands using organometallic vapor phase epitaxy (OMVPE). After a small layer is grown, typically less than 100 nm, the GaN becomes strain free. At this point, growth conditions are modified to encourage lateral growth and coalescence of islands into a continuous GaN film.

Island size is critical in controlling both the elastic compliance (the amount of lattice mismatch absorbed) and the characteristic decay length of the strain energy. The nanoscale pillars also appear to undergo a reduction in melting point, which effectively softens the islands during selective growth, according to UNM researcher Dr. David Zubia, leading to enhanced strain partitioning and reduced strain energy. Traditional patterns with pillar diameters 1 to 10 µm showed a decrease in defect density but were too large to absorb lattice strain. Optimum diameters appear to be less than 300 nm, Zubia said.

----------------
Figure 2. High-resolution TEMs of (a) GaN/Si heterinterface and (b) GaN away from the interface indicate that faults do not propagate into the GaN epilayer. (Source: University of New Mexico)

Though interfacial defects were not eliminated, TEMs indicated that stacking faults visible in the GaN layer near the interface were localized to within 20 to 50 nm from the interface and do not propagate into the GaN epilayer (Fig 2). Furthermore, there were indications that much of the mismatch strain was being taken up by the silicon. For example, segmented silicon lattice planes were within a 2 nm thick highly defected layer at the interface and in some areas penetrated as much as three lattice planes (0.95 nm) into the layer. Above this "defect region," the high quality of the epitaxial layer was verified with photoluminescence (PL), displaying PL intensity an order of magnitude higher for NHE GaN layers than from layers grown on substrates with no micro-pillars present. While more work remains to be done, the initial results with GaN on SOI are very promising and eventually may lead to availability of cheap, large-area GaN on SOI "substrates." Zubia anticipates devices fabricated on the pattern SOI substrates will be comparable to those grown on lateral-epitaxial-overgrowth substrates. Ultimately, the goal is to create threading defect-free islands and coalesce them without defects at the coalescence regions. Currently, threading defects appear to be under control, but coalescence defects are still under study, according to Zubia.

While the researchers have successfully demonstrated NHE's effectiveness on GaN layers on SOI, they are even more optimistic about GaAs and Ge on silicon because of the smaller mismatch. NHE looks to be a significant step toward realization of a manufacturable process for combining electronic and optical components on a common substrate. •